Typically, an integrated circuit package comprises an integrated circuit, having a combination of interconnected circuit elements inseparably associated on or within a continuous substrate referred to as a semiconductor die, the semiconductor die being encapsulated with n a ceramic or plastic package. The integrated circuit package comprises a number of connectors extending from the package for interconnection with external components upon a printed circuit board or like element. A special form of integrated circuit package, or IC, is a quad flat pack, or QFP. A QFP is a substantially square IC having numerous connectors extending from each side thereof.
To connect the semiconductor die to the connectors, it is known to provide a leadframe which extends the electrical connection from the relatively closely spaced input/outputs, terminating at bond pads, on the semiconductor die to the relatively widely spaced pads, on the semiconductor die to the relatively widely spaced connectors of the integrated circuit package. The leadframe can be considered to essentially form the skeleton of the integrated circuit package, comprising a number of closely spaced conductive interconnect leads.
In the semiconductor industry the trend has been to increase the density of integrated circuit packages, thus increasing the functionality of the IC. The technology at the semiconductor level has been advancing at a great rate in contrast to the mechanical technology involved in packaging these state-of-the-art devices. Unfortunately, the state of the mechanical technology is often the limiting factor in the obtainable density of the ICs. For example, some Very Large Scale Integration (VLSI) chips have as many as 256 interconnect leads evenly spaced around a package which is just over one inch square. This can result in the space between interconnect leads being only 0.008 inches. This presents considerable challenges as each conductive lead must be connected to a bondpad on the edge of a semiconductor which is only 0.35 to 0.45 inches square. The spacing, or pitch, between each bondpad is also very small, in the order of 0.006 inches. Thus the spacing between each conductive lead gets smaller as they approach the semiconductor.
Typically, the interconnect leads of the leadframe are made from flat sheets of copper which are photochemically treated to form a leadframe pattern thereon. The sheets of copper are then chemically etched to remove unwanted copper from between the interconnect leads. There is naturally a limit as to how small the space can be between each conductive lead and a limit as to how narrow a conductive lead can be and still be useable with current bonding techniques. A further constraint is that the angle at which the conductive lead approaches the semiconductor must substantially match the angle at which the bond wire extends therefrom in order to prevent the bond wire contacting more than one conductive lead during the bonding process.
Therefore, as QFP connector counts increase as a result of increased functionality of the integrated circuits contained therein, the internal leadframe design becomes a critical assembly yield and component quality issue. Any design optimization of the leadframe requires a trade-off between wire bond lengths to the semiconductor die, wire bond angles (i.e. the angle which a wire bonding lead and a conductive lead form) and bondtarget widths at the tip of the interconnect leads. Excessive bond lengths can result in wire shorting during molding of the integrated circuit package, while large bond angles on small bondtargets increase the probability of edge bonding which in turn will limit component assembly yields.
Thus, a disadvantage with the conventional design is that there is no direct control over desired bond lengths or bond angles. In general, the semiconductor die is not considered in the design process of the leadframe and therefore the conventional leadframe design approach does not optimize the leadframe in consideration of desired bond lengths or bond angles.